(1) Field of the Invention
The invention relates to a test structure and method to locate bridging defects in an integrated circuit device, and, more particularly, to a test structure and method to locate bridging defects and to monitor critical dimensions using passive voltage contrast without probing.
(2) Description of the Prior Art
Integrated circuit device manufacture requires the formation of material films on the surface of a wafer substrate. These material films are deposited and then patterned. Typical patterning techniques employ a photolithographic step (photo) and an etching step (etch) as is well known in the art. For example, in the formation of the metal interconnect level, a metal material such as aluminum is deposited over the substrate. A photo step is then used to form a patterned photoresist mask overlying the metal. An etch step is then performed where the metal is exposed to an etching atmosphere. The metal layer is etched through where exposed by the masking layer but not etched where protected by the masking layer. In this way, the metal is patterned to form the intended interconnect design for the metal level of the device.
Following the etching step, it is typical in the art to perform an inspection. Until recently, this inspection, called an after etch (AE) inspection, would be performed using an automated visual inspection system. This inspection system would optically analyze the AE wafer and compare the pattern to the design data.
A recent innovation is the use of the scanning electron microscope (SEM) to provide additional AE inspection information. A SEM works by scanning an area of the wafer with an incident, or primary, electron beam. A receiver in the SEM then captures secondary emitted electrons from the wafer. The captured emitted electrons are then analyzed with respect to the scanning beam to generate a visual image of the wafer surface.
Of particular interest for the present invention is a phenomenon of SEM imaging of integrated circuits called passive voltage contrast (PVC). PVC occurs when the SEM low-energy, primary electron beam strikes a conductive layer, such as metal or polysilicon. It has been found that conductive lines that are coupled to ground will emit a large amount of secondary electrons. Conversely, conductive lines that are floating will exhibit much lower electron emission. Therefore, ground interconnect lines will appear as bright lines on the SEM image screen while floating will appear as dark lines.
Referring now to FIG. 1, a conventional, interconnect layer, test structure is shown. This test structure is used for detecting bridging defects. The test structure comprises a patterned conductive layer 14 overlying a region of the substrate 10. The layer 14 is patterned to form a comb structure. The comb structure comprises a first network 18 of interconnected polygons originating at PAD A 24 and a second network 22 of interconnected polygons originating at the PAD B 26. The comb structure is further defined by interleaving of the first and second networks 18 and 22 such that parallel conductive lines are generated using the minimum spacing for the process.
After etching, the test structure can be electrically tested by probing both PAD A 24 and PAD B 26. A high resistance value between PAD A 24 and PAD B 26 indicates that the etching process for the conductive layer 14 has been complete such that the first network 18 and the second network 22 are independent. A low resistance value between PAD A 24 and PAD B 26 indicates that a short circuit exists between the networks 18 and 22. A typical cause for such a short circuit is incomplete etching of the conductive layer 14 that results in a bridging defect between the networks.
Referring now to FIG. 2, a SEM may be used to analyze the test structure using the PVC effect. In this case, the after etch wafer is loaded into the SEM system. For example, PAD B 26 is probed so that it can be coupled to ground. PAD A 24 is left floating. The PVC test is run by scanning a low-energy, primary electron beam on both first network 18 and second network 22. The first network 18 should remain dark where no bridging defect exists. However, the second network 22 will glow due to the defect. In this way, the PVC test can be used to detect if a bridging defect has occurred.
The prior art test structure has a serious limitation, however. As discussed above, the comb structure is formed by continuous, parallel lines. If a bridging defect occurs, then all of the parallel lines will be glowing. It is very difficult to visually identify the location of the defect 30, which can be very small, due to so much light emission from the rest of the structure. It is desirable to be able to precisely locate the bridging defect 30 for further failure analysis of the defect. For example, the defect can be cross-sectioned and analyzed using the SEM. However, this cross-sectioning must be performed at the exact location of the defect. In addition, the location of the defect can tell the process engineer important information about the operation of the photo or etching processes. Providing a test structure with an improved capability for both detecting and locating a bridging defect is an important focus of the present invention.
Several prior art inventions relate to passive voltage contrast and methods to detect processing errors in an integrated circuit device. U.S. Pat. No. 6,236,222 B1 to Sur, Jr. et al discloses a method to detect metal to via misalignments using passive voltage contrast (PVC) on a scanning electron microscope (SEM). A test structure is disclosed. U.S. Pat. No. 6,201,240 B1 to Dotan et al describes a method and an apparatus to enhance SEM imaging using narrow energy banding. U.S. Pat. No. 6,001,663 to Ling et al teaches a method and structure to detect defect sizes in polysilicon and source-drain devices. A double bridge, test structure is implemented using resistor paths comprising various structures. Defect size can be determined by measuring resistivity. U.S. Pat. No. 4,855,253 to Weber discloses a method to detect random defects in an integrated circuit device.